The present invention relates generally to integrated circuit devices and, more particularly, to a non-volatile, piezoelectronic memory based on piezoresistive strain produced by piezoelectric remanence.
Complementary Field Effect Transistors (FETs) support the standard computer architecture (CMOS) currently used in logic and memory. FETs exploit high channel mobility to control few-carrier currents electrostatically. However, limitations in this highly successful technology are appearing at current and future device scales. In particular, the inability to operate with power supplies significantly below 1 volt (V) limits device speed because faster clock speeds imply unacceptably high power consumption. Thus, it would be highly desirable to develop new switches and memories enabling computer architectures operable at low voltages/powers and high speeds.